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MRF89XA
? Interrupt Requests (IRQ0 and IRQ1) during FIFO
3.6.3
FIFO CLEARING
operations include:
- FIFO Full: FIFOFULL interrupt source is high
when the last FIFO byte (that is, the entire
Table 3-3 below summarizes the status of the FIFO
when switching between different modes.
FIFO) is full; otherwise it is low.
- FIFO Overrun Clear: FOVRRUN flag is set
when a new byte is written by the user (in TX
or Stand-by modes) or the Shift register (in
RX mode) while the FIFO is full. Data is lost
TABLE 3-3:
STATUS OF FIFO WHEN
SWITCHING BETWEEN
DIFFERENT MODES OF THE
CHIP
and the flag should be cleared by writing a ‘ 1 ’
(note that the FIFO will be cleared).
- FIFO Empty: FIFOEMPTY interrupt source is
low when byte 0 (that is, whole FIFO) is
empty; otherwise, it is high.
When retrieving data from the FIFO,
Note:
From
Stand-by TX
To
FIFO
Status
Cleared
Comments
In Buffered mode,
FIFO cannot be
written in Stand-by
before TX
FIFOEMPTY is updated on CSDAT falling
edge (that is, when FIFOEMPTY is
updated to low state the currently started
read operation must be completed). In
other words, the FIFOEMPTY state must
be checked after each read operation for
a decision on the next one
Stand-by RX
RX TX
Not cleared In Packet mode,
FIFO can be
written in Stand-by
before TX
Cleared —
Cleared —
(FIFOEMPT Y = 1 : more byte(s) to read;
FIFOEMPTY = 0 : no more bytes to read).
- FIFO Threshold: FIFO_THRESHOLD interrupt
source’s behavior depends on the running
mode (TX, RX or Stand-by modes) and the
threshold itself can be programmed through
the FIFOCREG (B value). This behavior is
RX
TX
TX
Stand-by Not cleared In Packet and
Buffered modes,
FIFO can be read
in Stand-by after
RX
RX Cleared —
Stand-by Not cleared —
illustrated in Figure 3-14 .
Any
Sleep
Cleared
—
FIGURE 3-14:
THRESHOLD IRQ
3.6.4
FIFO AND INTERRUPT REGISTERS
SOURCE BEHAVIOR
The registers associated with FIFO and Interrupts are:
1
IRQ source
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GCONREG ( Register 2-1 )
DMODREG ( Register 2-2 )
FDEVREG ( Register 2-3 )
BRSREG ( Register 2-4 )
FLTHREG ( Register 2-5 )
FIFOCREG ( Register 2-6 )
FTXRXIREG ( Register 2-14 )
FTPRIREG ( Register 2-15 )
RSTHIREG ( Register 2-16 )
FILCREG ( Register 2-17 )
PFCREG ( Register 2-18 )
0
B
TX
RX and Stand-by
B+1 B+2
Number of
bytes in FIFO
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SYNCREG ( Register 2-19 )
RSTSREG ( Register 2-21 )
OOKCREG ( Register 2-22 )
FCRCREG ( Register 2-32 )
All the other interrupts through RSSI, SYNC, Payload,
WRITEBYTE, DCLK, PLL Lock are handled through
either of these interrupts discussed in the preceding
sections.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 71
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